\doxysection{EXTI\+\_\+\+Core\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_e_x_t_i___core___type_def}{}\label{struct_e_x_t_i___core___type_def}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}


This structure registers corresponds to EXTI\+\_\+\+Typdef CPU1/\+CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI\+\_\+\+D1/\+EXTI\+\_\+\+D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI\+\_\+\+D1 and EXTI\+\_\+\+D2 bases addresses are calculated to point to CPUx first register\+: IMR1 in case of EXTI\+\_\+\+D1 that is addressing CPU1 (Cortex-\/\+M7) C2\+IMR1 in case of EXTI\+\_\+\+D2 that is addressing CPU2 (Cortex-\/\+M4) Note\+: EXTI\+\_\+\+D2 and corresponding C2\+IMRx, C2\+EMRx and C2\+PRx registers are available for Dual Core devices only.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a695e55f00384807891566c63adb4f9e0}{IMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a273eac8a06ed2deb556d43fc560fc86a}{EMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a63d5791daf114a4dc1808a90e02c4090}{PR1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a6a62db9c06a83694e1006a1326cd1c3b}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a998f49229fd9fc0bbf771269dd1d3ed5}{IMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_ae002893d8b632dee35f0a96b06985ac7}{EMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a12ac69a9ccf01834e65f550caa879308}{PR2}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a2e4dfb14aba05d9069e60ae55b68ed79}{RESERVED2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_abf7445f1040fdb761a32d7cd4b7d6352}{IMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a25bea2fd90f5db8ccdb0fa1281e3af35}{EMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___core___type_def_a30f7a99728ff2270ad0c2e47c12bc1f8}{PR3}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
This structure registers corresponds to EXTI\+\_\+\+Typdef CPU1/\+CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI\+\_\+\+D1/\+EXTI\+\_\+\+D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI\+\_\+\+D1 and EXTI\+\_\+\+D2 bases addresses are calculated to point to CPUx first register\+: IMR1 in case of EXTI\+\_\+\+D1 that is addressing CPU1 (Cortex-\/\+M7) C2\+IMR1 in case of EXTI\+\_\+\+D2 that is addressing CPU2 (Cortex-\/\+M4) Note\+: EXTI\+\_\+\+D2 and corresponding C2\+IMRx, C2\+EMRx and C2\+PRx registers are available for Dual Core devices only. 

\label{doc-variable-members}
\Hypertarget{struct_e_x_t_i___core___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_e_x_t_i___core___type_def_a273eac8a06ed2deb556d43fc560fc86a}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!EMR1@{EMR1}}
\index{EMR1@{EMR1}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR1}{EMR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a273eac8a06ed2deb556d43fc560fc86a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+EMR1}

EXTI Event mask register, Address offset\+: 0x04 \Hypertarget{struct_e_x_t_i___core___type_def_ae002893d8b632dee35f0a96b06985ac7}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!EMR2@{EMR2}}
\index{EMR2@{EMR2}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR2}{EMR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_ae002893d8b632dee35f0a96b06985ac7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+EMR2}

EXTI Event mask register, Address offset\+: 0x14 \Hypertarget{struct_e_x_t_i___core___type_def_a25bea2fd90f5db8ccdb0fa1281e3af35}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!EMR3@{EMR3}}
\index{EMR3@{EMR3}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR3}{EMR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a25bea2fd90f5db8ccdb0fa1281e3af35} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+EMR3}

EXTI Event mask register, Address offset\+: 0x24 \Hypertarget{struct_e_x_t_i___core___type_def_a695e55f00384807891566c63adb4f9e0}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!IMR1@{IMR1}}
\index{IMR1@{IMR1}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR1}{IMR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a695e55f00384807891566c63adb4f9e0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+IMR1}

EXTI Interrupt mask register, Address offset\+: 0x00 \Hypertarget{struct_e_x_t_i___core___type_def_a998f49229fd9fc0bbf771269dd1d3ed5}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!IMR2@{IMR2}}
\index{IMR2@{IMR2}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR2}{IMR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a998f49229fd9fc0bbf771269dd1d3ed5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+IMR2}

EXTI Interrupt mask register, Address offset\+: 0x10 \Hypertarget{struct_e_x_t_i___core___type_def_abf7445f1040fdb761a32d7cd4b7d6352}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!IMR3@{IMR3}}
\index{IMR3@{IMR3}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR3}{IMR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_abf7445f1040fdb761a32d7cd4b7d6352} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+IMR3}

EXTI Interrupt mask register, Address offset\+: 0x20 \Hypertarget{struct_e_x_t_i___core___type_def_a63d5791daf114a4dc1808a90e02c4090}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!PR1@{PR1}}
\index{PR1@{PR1}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR1}{PR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a63d5791daf114a4dc1808a90e02c4090} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+PR1}

EXTI Pending register, Address offset\+: 0x08 \Hypertarget{struct_e_x_t_i___core___type_def_a12ac69a9ccf01834e65f550caa879308}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!PR2@{PR2}}
\index{PR2@{PR2}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR2}{PR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a12ac69a9ccf01834e65f550caa879308} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+PR2}

EXTI Pending register, Address offset\+: 0x18 \Hypertarget{struct_e_x_t_i___core___type_def_a30f7a99728ff2270ad0c2e47c12bc1f8}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!PR3@{PR3}}
\index{PR3@{PR3}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR3}{PR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a30f7a99728ff2270ad0c2e47c12bc1f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+PR3}

EXTI Pending register, Address offset\+: 0x28 \Hypertarget{struct_e_x_t_i___core___type_def_a6a62db9c06a83694e1006a1326cd1c3b}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a6a62db9c06a83694e1006a1326cd1c3b} 
uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, 0x0C \Hypertarget{struct_e_x_t_i___core___type_def_a2e4dfb14aba05d9069e60ae55b68ed79}\index{EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!EXTI\_Core\_TypeDef@{EXTI\_Core\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___core___type_def_a2e4dfb14aba05d9069e60ae55b68ed79} 
uint32\+\_\+t EXTI\+\_\+\+Core\+\_\+\+Type\+Def\+::\+RESERVED2}

Reserved, 0x1C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
